1. Field of the Invention
Generally, the present disclosure relates to the field of fabricating microstructure devices, and, more particularly, to techniques for enhancing product yield by reducing the defect rate caused by metal contamination at several process stages during the formation of complex microstructures, such as integrated circuits and the like.
2. Description of the Related Art
Today's global market forces manufacturers of mass products to offer high quality products at a low price. It is thus important to improve yield and process efficiency to minimize production costs. This holds especially true in the field of fabricating microstructures having a complex configuration, such as advanced integrated circuits, since here it is essential to combine cutting edge technology with mass production techniques. It is, therefore, the goal of manufacturers of microstructures to reduce the consumption of raw materials and consumables while at the same time improve process tool utilization. The latter aspect is especially important since, in modern semiconductor facilities, equipment is required, which is extremely cost intensive and represents the dominant part of the total production costs. Consequently, high tool utilization, in combination with a high product yield, i.e., with a high ratio of good devices and faulty devices, results in increased profitability.
Complex microstructures, such as integrated circuits, are typically manufactured in automated or semi-automated facilities, thereby passing through a large number of process and metrology steps to complete the device. The number and the type of process steps and metrology steps a semiconductor device has to go through depends on the specifics of the device to be fabricated. For example, a usual process flow for an integrated circuit, which may be considered as a representative of a complex microstructure, may include a plurality of photolithography steps to image a circuit pattern for a specific device layer into a resist layer, which is subsequently patterned to form a resist mask used in further processes for forming device features in the device layer under consideration by, for example, etch, implant, deposition, polish processes and the like. Thus, layer after layer, a plurality of process steps are performed based on a specific lithographic mask set for the various layers of the specified device. For instance, a sophisticated CPU requires several hundred process steps, each of which has to be carried out within specified process margins to fulfill the specifications for the device under consideration. Since many of these processes are very critical, a plurality of metrology steps have to be performed to efficiently control the process flow. Typical metrology processes may include the measurement of layer thickness, the determination of dimensions of critical features, such as the gate length of transistors, the measurement of dopant profiles, the number, the size and the type of defects, and finally the electrical characteristics, which may represent the contribution of a plurality of process stages and which may finally decide whether a device is an operational device or a faulty device.
In a semiconductor facility, a plurality of different product types are usually manufactured at the same time, such as memory chips of different design and storage capacity, CPUs of different design and operating speed and the like, wherein the number of different product types may even reach one hundred and more in production lines for manufacturing ASICs (application specific ICs). Since each of the different product types may require a specific process flow, different mask sets for the lithography, specific settings in the various process tools, such as deposition tools, etch tools, implantation tools, chemical mechanical polishing CMP) tools, metrology tools and the like may be necessary. Consequently, the process flow in the facility may be very complex, since many re-entrant processes, i.e., a repeated use of the same process tools at different manufacturing stages of a specific type of product, and many predictable and non-predictable events may occur during the manufacturing processes and the various metrology processes.
Due to the continuous shrinkage of feature sizes of the circuit elements, such as the gate length of field effect transistors and the like, a plurality of tightly set process margins and specifications have to be fulfilled during the complex manufacturing process in order to obtain the required functionality, speed and reliability of the final semiconductor devices. A significant deviation from these tightly set specifications, which may be caused by any type of process fluctuations, contaminations and the like, may have a direct influence on the finally obtained device parameters, such as overall performance of circuit elements, the time to electrical breakdown, failure caused by electromigration and the like. For example, metal contaminations created in corresponding dielectric and/or semiconductive areas of semiconductor devices have been a concern during recent decades in the microelectronic industry. For instance, the presence of metal contaminations in semiconductor areas may result in additional electronic state in the band gap of the corresponding semiconductor material, thereby, for instance, reducing lifetime of minority charge carriers and the like. Furthermore, the incorporation of metal contaminations into sensitive dielectric areas, such as gate dielectric materials, may considerably alter the dielectric behavior of these materials, thereby contributing to increased leakage currents. Corresponding effects are even further exacerbated in highly sophisticated semiconductor devices in which corresponding dielectric materials approach physical limits, wherein only a few atomic layers may be provided for sophisticated dielectric materials. Similarly, the incorporation of undesired metal species in doped semiconductor areas may result in modified junction behavior, thereby also contributing to increased diode leakage currents, which in turn may also contribute to dynamic and static leakage currents. For this reason, great efforts have been made in order to monitor the degree of metal contamination throughout the entire manufacturing process flow, in particular as highly conductive metals such as copper are increasingly used in sophisticated semiconductor devices. As is well known, copper readily diffuses in a plurality of dielectric materials, such as silicon dioxide and the like, and also in silicon, wherein even minute amounts of copper may have a significant influence on the overall device performance, as explained above.
The problem of metal contamination may further be exacerbated by the fact that any process tools, such as process tools for performing wet chemical treatment, such as etching, resist strip and the like, may be used at several stages of the entire process flow in view of enhancing overall process tool utilization, as discussed above. For example, at many stages of the overall manufacturing flow, resist material may have to be applied, patterned and used as a mask for etch processes, implantation processes and the like, wherein a subsequent removal of the resist mask may be accomplished on the basis of plasma-based or wet chemical-based etch processes. Similarly, in many stages of the overall process flow, sophisticated cleaning processes, for instance for removing organic contaminations, particles and the like, may have to be performed, for instance on the basis of wet chemical treatments, while in other cases surface areas of the substrates may have to be patterned on the basis of wet chemical etch chemistries. Also, in this case, the same process tool may be used at several very different stages of the overall manufacturing flow, thereby contributing to an increased probability of introducing undesired metal species into the corresponding process chambers and/or process liquids used for establishing an appropriate process ambient. In order to monitor the status of the various process tools and thus of the substrates to be processed in these tools, corresponding measurements may be performed on a regular basis in order to identify metal species that may be present in the various process chambers and process liquids. For this purpose, sophisticated monitoring techniques have been established, such as TXRF (total reflectance x-ray fluorescence), ICPMS (inductively coupled mass spectrometry) and the like. For example, in a TXRF metrology process, a smooth surface portion of a test substrate may be exposed to a probing x-ray beam that is incident on a small angle, thereby resulting in a substantially total reflectance of the incoming beam. On the other hand, atoms in the vicinity of the surface may be excited by the x-ray beam, which may cause a respective secondary radiation that is detected by a solid body detector, thereby enabling characteristic spectra to enable detection of type and amount of characteristic metal species. In order to further enhance sensitivity of this measurement technique, the sample surface may be appropriately prepared by vapor phase decomposition in which the sample surface may be treated on the basis of hydrofluoric acid, thereby dissolving any surface oxide of the sample wafer together with corresponding metal contaminants. The resulting droplets that are condensed on the sample surface may then be further analyzed by TXRF, thereby obtaining enhanced sensitivity. In other cases, the resulting droplets may be evaporated and may be analyzed by spectrometry, wherein even further enhanced sensitivity may be achieved, while, however, efforts with respect to preparing the sample and preparing the overall measurement procedure may be increased compared to the above-explained x-ray measurement techniques. In this manner, an overview of the different metals, such as cadmium, cer, aluminum, lead, copper and the like, may be obtained for the corresponding process liquids used in the process tools. For obtaining relative measurement results with respect to the metal contamination, the vapor phase decomposition process in combination with the subsequent actual analysis technique may require high efforts in terms of delay for obtaining the measurement results and also in terms of production costs due to the requirement of sample wafers and significant resources with respect to process engineers.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.